1. Technical Field
The present invention relates to a level-shifter circuit and a memory device comprising said circuit.
2. Description of the Related Art
In the prior art, level-shifter circuits are known that enable low-voltage devices to interface with high-voltage components.
In particular, so-called negative shifters are known that are suitable for shifting the low-voltage control signals to negative high voltages. Said shifters are often used in memories, especially in the flash memory cells in which particularly negative voltages are used to delete the cells. The result is that the transistors belonging to the negative-level shifters are polarized in stress conditions by the channel oxide. Further, the transistors forming part of the circuitry controlled by the aforesaid shifters have high voltages at the heads of the oxide.
A negative-level shifter is disclosed in the diagram in FIG. 1. Said shifter comprises a pair of PMOS transistors M20-M21 having gate terminals in common and connected to ground GND, source terminals connected to the outputs of two inverters 10 and 11 which are connected in series and have an input signal In, and drain terminals connected to the drain terminals of pair of NMOS transistors M22-M23 having gate terminals in common and source terminals connected to the polarization voltage VNEG. The source terminals of the NMOS transistors M22-M23 are connected to drain terminals of another two NMOS transistors M24, M25 having respective gate terminals connected to the drain terminals of the transistors M25 and M24; and the drain terminal of the transistor M25 is the output OUT of the level-shifter. Said negative level shifter, although it does not have transistors under stress, loses the ability to switch if the voltage VNEG becomes zero.